[IEEE] A Low-Latency and Low-Power Approach for Coherency and Memory Protocols on PCI Express 6.0 PHY at 64.0 GT/s With PAM-4 Signaling

rk9524 Post time 2024-4-20 21:56:25 | Show all posts |Read mode
Reward10points

journal£ºIEEE Micro

Authors£ºDebendra Das Sharma

Published date£º2022-3-1

DOI£º10.1109/mm.2021.3137807

PDF link£ºhttps://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=9662217

Article link£ºhttp://dx.doi.org/10.1109/mm.2021.3137807

Article Source£ºInstitute of Electrical and Electronics Engineers (IEEE)¡£


Remark£º

Best Answer

Reply

Use magic Donate Report

All Reply2 Show all posts
gaoblue1608 Post time 2024-4-20 21:56:26 | Show all posts

This post has been completed

Completed attachments will be deleted within 24 hours.
Reply

Use magic Donate Report

rk9524 Post time 2024-4-21 00:15:50 | Show all posts

This post has been completed

Completed attachments will be deleted within 24 hours.
Reply

Use magic Donate Report


Junior Member
  • post

  • reply

  • points

    230

Latest Reply



Return to the list