[Other] Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

 Close Closed
Joyprokash Post time 2024-4-17 21:09:25 | Show all posts |Read mode
Reward20points

journal£ºECS Journal of Solid State Science and Technology

Authors£ºChandana Anguru; Vamsi Krishna Aryasomayajula; Venkata Ramakrishna Kotha; Sresta Valasa; Sunitha Bhukya; Narendar Vadthiya; V. Bheemudu; Sagar Kallepelli; Satish Maheshwaram; Praveen Kumar Mudidhe

Published date£º2024-1-1

DOI£º10.1149/2162-8777/ad15a8

PDF link£ºhttps://iopscience.iop.org/article/10.1149/2162-8777/ad15a8

Article link£ºhttp://dx.doi.org/10.1149/2162-8777/ad15a8

Article Source£ºThe Electrochemical Society¡£


Remark£º
Reply

Use magic Donate Report

All Reply0 Show all posts

Reply

You have to log in before you can reply Login | Register

Points Rules

Intermediate member
  • post

  • reply

  • points

    420

Latest Reply



Return to the list