[Other] Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node

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firas365 Post time 2024-5-4 17:28:13 | Show all posts |Read mode
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journal£ºECS Journal of Solid State Science and Technology

Authors£ºSresta Valasa; Shubham Tayal; Laxman Raju Thoutam

Published date£º2022-4-1

DOI£º10.1149/2162-8777/ac6627

PDF link£ºhttps://iopscience.iop.org/article/10.1149/2162-8777/ac6627

Article link£ºhttp://dx.doi.org/10.1149/2162-8777/ac6627

Article Source£ºThe Electrochemical Society¡£


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