Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis

Post time 2024-4-30 14:36:34

journal：2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)

Authors：Shivendra Singh; Ekta Tiwari; Abhinav Gupta; Sneh Saurabh

Published date：2024-1-6

DOI：10.1109/vlsid60093.2024.00009

PDF link：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=10483466

Article link：http://dx.doi.org/10.1109/vlsid60093.2024.00009

Article Source：IEEE。

Remark：

Post time 2024-4-30 14:36:58

: Waiting for confirmation
If the PDF has not been accepted after 72 hours, the system will automatically adopt it.

[IEEE] Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis

Same Category

Latest Reply

Announcement

Enthusiastic users today

[IEEE] Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis Copy

Same Category

Latest Reply

Announcement

Enthusiastic users today

[IEEE] Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis